`timescale 1ns/1ns

module mul_tb;
    reg signed [7:0] i_a;
    reg signed [7:0] i_b;
    
    wire signed [15:0] o_mul;

    initial begin
        $dumpfile("output/mul_tb.vcd");
        $dumpvars(0, mul_tb);
    end
    
    initial begin
        #10;
        i_a = 10;
        i_b = 20;
        #10;
        i_a = -10;
        i_b = 20;
        #10;
        i_a = -10;
        i_b = -20;
        #10;
        i_a = 80;
        i_b = 90;
        #10;
        i_a = -80;
        i_b = -90;
        #10;
        i_a = 127;
        i_b = 127;
        #10;
        i_a = -127;
        i_b = -127;
        #10;
        i_a = 255;
        i_b = 255;
        #10;
        i_a = -255;
        i_b = -255;
        #100 $stop;
    end
    
    mul mul_inst(
    .iA   (i_a),
    .iB   (i_b),    
    .oMul (o_mul)   
    );
 
endmodule